1. Field of the Invention
The present invention generally relates to a chip package structure, and more particularly, to a chip package structure with high voltage protection.
2. Description of Related Art
When a chip package structure with high-voltage input (for example, a power module for controlling a power supply or an IGBT module for controlling a driving motor) is designed, in order to make sure that the chip package structure meets the safety specification (for example, the UL standard) and works properly, the creepage distance and clearance distance between a voltage input terminal (for example, a lead) and a metal material (for example, a heat dissipation device) of the chip package structure are usually taken into consideration so that short circuit between the lead and the heat dissipation device is prevented and a transient high voltage input from the lead will not jump directly to a low voltage terminal (i.e., the heat dissipation device) or accordingly threaten a user's safety.
FIG. 1 is a cross-sectional view of a conventional high-power chip package structure. FIGS. 2A and 2B are cross-sectional views illustrating a fabrication process of the chip package structure in FIG. 1. Referring to FIG. 1, the conventional chip package structure 100 has a substrate 110, a plurality of chips 120, a heat dissipation device E, a plurality of leads 130, a casing 140, a silicon layer 150, and a cover 160. The substrate 110 has two surfaces 112 and 114 which are opposite to each other. The chips 120 are disposed on the surface 112, and the heat dissipation device E is disposed on the surface 114. The casing 140 is disposed on the surface 112, and the casing 140 has two surfaces 141 and 142 which are opposite to each other, an opening 143 on the surface 141, and an opening 144 on the surface 142. The opening 143 exposes a surface of the heat dissipation device E away from the substrate 110, and the opening 144 exposes the chips 120 on the substrate 110.
The leads 130 are L-shaped and pass through the casing 140. A first end 132 of each of the leads 130 is located within the opening 144, and a second end 134 of each of the leads 130 is extended out from the surface 142. The connections between the chips 120, the connections between the chips 120 and the substrate 110, and the connections between the chips 120 and the leads 130 are accomplished through a plurality of bonding wires 170. The silicon layer 150 is disposed in the opening 144 and encapsulates the chips 120 and the bonding wires 170, and the cover 160 is disposed on the silicon layer 150 and covers the opening 144.
The fabrication method of the conventional chip package structure 100 is described below. First, referring to FIG. 2A, the leads 130 are fabricated in the casing 140, wherein the leads 130 may be placed into a mold first and then formed integrally with the casing 140 through injection molding, or the casing 140 may be first formed through injection molding and the leads 130 are then embedded into the casing 140. Next, referring to FIG. 2B, the heat dissipation device E is disposed on the surface 114 of the substrate 110, and the chips 120 are then disposed on the surface 112 of the substrate 110 and connected to the substrate 110 and to each other through wire bonding. After that, the casing 140 is disposed on the surface 112 of the substrate 110 and is adhered to the substrate 110, wherein the opening 144 of the casing 140 exposes part of the surface 112 of the substrate 110 and the chips 120, and the opening 143 of the casing 140 exposes a surface of the heat dissipation device E. Thereafter, the chips 120, the substrate 110, and the leads 130 are connected through wire bonding. Next, referring to FIG. 1 again, silica gel is filled into the opening 144 to form the silicon layer 150. Finally, the cover 160 is disposed on the silicon layer 150, and the opening 144 is sealed.
Because the leads 130 are extended out from the surface 142 and the surface 142 is opposite to the surface 141 on which the heat dissipation device E is disposed, the creepage distance and the clearance distance of the conventional chip package structure 100 are very large. As a result, the chip package structure 100 can meet the safety requirements while the chip package structure 100 has a need of high voltage input. However, the fabrication process of the conventional chip package structure 100 is very complicated, and since the casing 140 and the chips 120 are all disposed on the surface 112 of the substrate 110, the substrate 110 has very small surface area for disposing the chips 120. In order to increase the surface area of the substrate 110 for disposing the chips 120, the size of the substrate 110 has to be increased. As a result, both the cost of the substrate 110 and the volume of the chip package structure 100 are increased.